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FEATURES 150 MSPS Encode Rate Low Input Capacitance: 17 pF Low Power: 750 mW -5.2 V Single Supply MIL-STD-883 Compliant Versions Available APPLICATIONS Radar Systems Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal Intelligence
High-Speed 8-Bit Monolithic A/D Converter AD9002
FUNCTIONAL BLOCK DIAGRAM
OVERFLOW INHIBIT ANALOG IN R +VREF R
255 256
AD9002
OVERFLOW BIT 8 (MSB) D E C O D I N G L O G I C
BIT 7 BIT 6 BIT 5
R
128
R/2 REFMID R/2
127
L A T C H
BIT 4 BIT 3
R
GENERAL DESCRIPTION
2
BIT 2 BIT 1 (LSB)
The AD9002 is an 8-bit, high-speed, analog-to-digital converter. The AD9002 is fabricated in an advanced bipolar process that allows operation at sampling rates in excess of 150 megasamples/ second. Functionally, the AD9002 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ECL compatible output latches. An exceptionally wide large signal analog input bandwidth of 160 MHz is due to an innovative comparator design and very close attention to device layout considerations. The wide input bandwidth of the AD9002 allows very accurate acquisition of high speed pulse inputs, without an external track-and-hold. The comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. The AD9002 provides an external hysteresis control pin that can be used to optimize comparator sensitivity to further improve performance. Additionally, the AD9002's low power dissipation of 750 mW makes it usable over the full extended temperature range. The AD9002 also incorporates an overflow bit to indicate overrange inputs. This overflow output can be disabled with the overflow inhibit pin.
R -VREF ENCODE ENCODE GND HYSTERESIS -VS
1
The AD9002 is available in two grades, one with 0.5 LSB linearity and one with 0.75 LSB linearity. Both versions are offered in an industrial grade, -25C to +85C, packaged in a 28-lead DIP and a 28-leaded JLCC. The military temperature range devices, -55C to +125C, are available in ceramic DIP and LCC packages and comply with MIL-STD-883 Class B.
REV. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD9002-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (-V = -5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
S
Parameter RESOLUTION DC ACCURACY Differential Linearity Integral Linearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Bias Current1 Input Resistance Input Capacitance Large Signal Bandwidth2 Input Slew Rate3 REFERENCE INPUT Reference Ladder Resistance Ladder Temperature Coefficient Reference Input Bandwidth DYNAMIC PERFORMANCE Conversion Rate Aperture Delay Aperture Uncertainty (Jitter) Output Delay (tPD)4, 5 Transient Response6 Overvoltage Recovery Time7 Output Rise Time4 Output Fall Time4 Output Time Skew4, 8 ENCODE INPUT Logic "1" Voltage4 Logic "0" Voltage4 Logic "1" Current Logic "0" Current Input Capacitance Encode Pulsewidth (Low)9 Encode Pulsewidth (High)9 OVERFLOW INHIBIT INPUT 0 V Input Current AC LINEARITY10 Effective Bits11 In-Band Harmonics dc to 1.23 MHz dc to 9.3 MHz dc to 19.3 MHz Signal-to-Noise Ratio12 Two Tone Intermod Rejection13 DIGITAL OUTPUTS4 Logic "1" Voltage Logic "0" Voltage POWER SUPPLY14 Supply Current (-5.2 V) Nominal Power Dissipation Reference Ladder Dissipation Power Supply Rejection Ratio15
Temp
AD9002AD/AJ Min Typ Max 8
AD9002BD/BJ Min Typ Max 8
AD9002SD/SE Min Typ Max 8
AD9002TD/TE Min Typ Max 8
Unit Bits
25C Full 25C Full Full 25C Full 25C Full Full 25C Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full Full Full Full 25C 25C 25C Full 25C 25C 25C 25C 25C 25C Full Full 25C Full 25C 25C 25C
0.75 1.0 0.6 1.0 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 -1.1 -1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 14 17 10 12
0.6
0.5 0.75 0.4 0.5 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 -1.1 -1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 14 17 10 12
0.4
0.75 1.0 0.6 1.0 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 -1.1 -1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 14 17 10 12
0.6
0.5 0.75 0.4 0.5 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 -1.1 -1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 22 14 17 10 12
0.4
LSB LSB LSB LSB
mV mV mV mV V/C A A k pF MHz V/s /C MHz MSPS ns ps ns ns ns ns ns ns V V A A pF ns ns A Bits dB dB dB dB dB V V mA mA mW mW mV/V
22
22
22
40
110
40
110
40
110
40
110
125 2.5
125 5.5 3.0 2.5 2.5
125 5.5 3.0 2.5 2.5
125 5.5 3.0 2.5 2.5
5.5 3.0 2.5
-1.1 -1.5 145 750 50 0.8 175 200 1.5
-1.1 -1.5 145 750 50 0.8 175 200 1.5
-1.1 -1.5 145 750 50 0.8 175 200 1.5
-1.1 -1.5 145 750 50 0.8 175 200 1.5
NOTES 1 Measured with AIN = 0 V. 2 Measured by FFT analysis where fundamental is -3 dBc. 3 Input slew rate derived from rise time (10 to 90%) of full scale input. 4 0utputs terminated through 100 to -2 V. 5 Measured from ENCODE in to data out for LSB only. 6 For full-scale step input, 8-bit accuracy is attained in specified time. 7 Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage. 8 Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences. 9 ENCODE signal rise/fall times should be less than 10 ns for normal operation. 10 Measured at 125 MSPS encode rate. 11 Analog input frequency = 1.23 MHz. 12 RMS signal to rms noise, with 1.23 MHz analog input signal. 13 Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz. 14 Supplies should remain stable within 5% for normal operation. 15 Measured at -5.2 V 5%. Specifications subject to change without notice.
-2-
REV. 0
AD9002
ABSOLUTE MAXIMUM RATINGS 1 Recommended Operating Conditions
Supply Voltage (-VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . -6 V Analog-to-Digital Supply Voltage Differential . . . . . . . . 0.5 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . -VS to +0.5 V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -VS to 0 V Reference Input Voltage (+VREF - VREF)2 . . . -3.5 V to +0.1 V Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . 4 mA ENCODE to ENCODE Differential Voltage . . . . . . . . . . . 4 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature Range AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . -25C to +85C AD9002SE/SD/TD/TE . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300C
NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 +VREF -VREF under all circumstances. 3 Maximum junction temperature (t J max) should not exceed 175C for ceramic packages, and 150C for plastic packages: tJ = PD (JA) + tA PD (JC) + tC where PD = power dissipation JA = thermal impedance from junction to ambient (C/W) JC = thermal impedance from junction to case (C/W) tA = ambient temperature (C) tC = case temperature (C) Typical thermal impedances are: Ceramic DIP JA = 56C/W; JC = 20C/W Ceramic LCC JA = 69C/W; JC = 23C/W PLCC JA = 60C/W; JC = 19C/W.
Input Voltage Parameter -VS +VREF -VREF Analog Input Min -5.46 -VREF -2.1 -VREF Nominal -5.20 0.0 V -2.0 Max -4.94 +0.1 +VREF +VREF
EXPLANATION OF TEST LEVELS
- 100% production tested. - 100% production tested at 25C, and sample tested at specified temperatures. Test Level III - Sample tested only. Test Level IV - Parameter is guaranteed by design and characterization testing. Test Level V - Parameter is a typical value only. Test Level VI - All devices are 100% production tested at 25C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
ORDERING GUIDE
Test Level I Test Level II
Model AD9002AD AD9002BD AD9002AJ AD9002BJ AD9002SD/883B AD9002SE/883B AD9002TD/883B AD9002TE/883B
Package Linearity Temperature Range Option* 0.75 LSB 0.50 LSB 0.75 LSB 0.50 LSB 0.75 LSB 0.75 LSB 0.50 LSB 0.50 LSB -25C to +85C -25C to +85C -25C to +85C -25C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C D-28 D-28 J-28 J-28 D-28 E-28A D-28 E-28A
*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip Carrier, J-Formed Leads.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9002 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. F
-3-
AD9002
FUNCTIONAL DESCRIPTION Pin # 1 2 Mnemonic DIGITAL GROUND OVERFLOW INH Description One of four digital ground pins. All digital ground pins should be connected together. OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs. Overflow Enabled (Floating or -5.2 V) of D1-D8 10 0 0 0 0 0 0 0 0XXXXX XXX
Analog Input VIN > +VREF VIN +VREF 3 4 5 6 7 8 9 10 11 12 13 14 15 16-19 20 21, 22 23 24, 25 26 27 HYSTERESIS +VREF ANALOG INPUT ANALOG GROUND ENCODE ENCODE ANALOG GROUND ANALOG INPUT -VREF REFMID DIGITAL GROUND DIGITAL -VS D1 (LSB) D2-D5 DIGITAL GROUND ANALOG -VS DIGITAL GROUND D6, D7 D8 (MSB) OVERFLOW
Overflow Inhibited (GND) of D1-D8 01 1 1 1 1 1 11
0XXXX XX XX
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change from -5.2 V to -2.2 V at the Hysteresis control pin. Normally converted to -5.2 V. The most positive reference voltage for the internal resistor ladder. One of two analog input pins. Both analog input pins should be connected together. One of two analog ground pins. Both analog ground pins should be connected together. Noninverted input of the differential encode input. This pin is driven in conjunction with ENCODE. Data is latched on the rising edge of the ENCODE signal. Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE. One of two analog ground pins. Both analog ground pins should be connected together. One of two analog input pins. Both analog inputs should be connected together. The most negative reference voltage for the internal resistor ladder. The midpoint tap on the internal resistor ladder. One of four digital ground pins. All digital ground pins should be connected together. One of two negative digital supply pins (nominally -5.2 V). Both digital supply pins should be connected together. Digital Data Output Digital Data Output One of four digital ground pins. All digital ground pins should be connected together. One of two negative analog supply pins (nominally -5.2 V). Both analog supply pins should be connected together One of four digital ground pins. All digital ground pins should be connected together. Digital Data Output Digital Data Output Overflow data output. Logic high indicates an input overvoltage (V IN > +VREF) if OVERFLOW INHIBIT is enabled (overflow enabled, -5.2 V). See OVERFLOW INHIBIT.
28
DIGITAL -VS
One of two negative digital supply pins (nominally -5.2 V). Both digital supply pins should be connected together.
PIN DESIGNATIONS
DIP
DIGITAL 1 GROUND OVERFLOW INH 2 HYSTERESIS 3 +VREF 4 ANALOG INPUT 5 ANALOG 6 GROUND ENCODE 7
28 27 26 25 24 23
LCC
DIGITAL GROUND DIGITAL -VS OVERFLOW D8(MSB) DIGITAL -VS OVERFLOW +VREF D8(MSB) D7 D6 HYSTERESIS OVERFLOW INH
JLCC
DIGITAL GROUND ANALOG -VS DIGITAL GROUND
ANALOG -VS
D7 D6
4
3
2
1 28 27 26
25 24 23 22 21 20 19
AD9002
TOP VIEW ENCODE 8 (Not to Scale) 21 ANALOG -VS ANALOG 9 20 DIGITAL GROUND GROUND 19 D5 ANALOG INPUT 10 -VREF 11 REFMID 12 DIGITAL 13 GROUND DIGITAL -VS 14
18 17 16 15
DIGITAL GROUND 22 ANALOG -VS
D5
18 17
D4 D3 D2 D1(LSB)
ANALOG INPUT 5 ANALOG GROUND 6 ENCODE 7 ENCODE 8 ANALOG 9 GROUND ANALOG INPUT 10 -VREF 11
25 24
AD9002
TOP VIEW (Not to Scale)
23 22 21 20 19
D7 D6 DIGITAL GROUND ANALOG -VS ANALOG -VS DIGITAL GROUND D5
D8(MSB) OVERFLOW DIGITAL -VS DIGITAL GROUND OVERFLOW INH HYSTERESIS +VREF
26 27 28 1 2 3 4 5 6 7 8 9 10 11
D4 D3 D2 D1(LSB) DIGITAL -VS DIGITAL GROUND REFMID
AD9002
TOP VIEW
(Not to Scale)
16 15 14 13 12
DIGITAL GROUND DIGITAL -VS
-4-
ENCODE ANALOG GROUND ANALOG INPUT -VREF
ANALOG GROUND
ANALOG INPUT
ENCODE
12 13 14 15 16 17 18
REFMID
D1(LSB) D2 D3
D4
REV. F
AD9002
N+1 ANALOG INPUT N APERTURE DELAY ENCODE N+2
t PD
OUTPUT DATA N-1 N N+1
Figure 1. Timing Diagram
AD9002
AD9002
+VREF R
AD9002
R/2 ENCODE ENCODE ANALOG INPUT -5.2V -5.2V R/2 DIGITAL OUTPUT R -VREF REFMID
-5.2V
-5.2V
-5.2V COMPARATOR CELLS
Figure 2. Input/Output Circuits
OVERFLOW INHIBIT HYSTERESIS DIGITAL GROUND
0.1 F -5.2V -VS HYSTERESIS OVERFLOW INH 100 AD1 AD2 1k AD3 -2V 0.1 F +VREF GROUND 1k ANALOG IN ENCODE ENCODE -VREF OVERFLOW D8 D7 D6 D5 D4
DIGITAL -VS OVERFLOW D8 (MSB)
+VREF
1k 1k 1k 1k 1k 1k 1k 1k D2 1k D1
ANALOG INPUT ANALOG GROUND ENCODE ENCODE ANALOG GROUND ANALOG INPUT
D7 D6 DIGITAL GROUND ANALOG -VS DIGITAL GROUND
AD9002
D3
D5 D4
STATIC BURN IN AD1 = 0V AD2 = ECL HIGH DYNAMIC BURN IN AD1
AD3 = ECL LOW 0V -2V ECL HIGH ECL LOW ECL HIGH
-VREF
D1 (LSB) DIGITAL GROUND DIGITAL REFMID -VS
D2
D3
AD2
Figure 4. Die Layout and Mechanical Information
AD3 ALL RESISTORS 5%, ALL CAPACITORS 20%, ALL SUPPLIES 5%
ECL LOW F
Figure 3. Burn-in Diagram
Die Dimensions . . . . . . . . . . . . . . . . . 106 x 114 x 15 ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic) Bond Wire . . . . . . . . . . . . . 1-1.3 mil Gold; Gold Ball Bonding -5-
REV. F
AD9002
APPLICATION INFORMATION LAYOUT SUGGESTIONS
The AD9002 is compatible with all standard ECL logic families, including 10K and 10KH. 100K ECL's logic levels are temperature compensated, and are therefore compatible with the AD9002 (and most other ECL device families) only over a limited temperature range. To operate at the highest encode rates, the supporting logic around the AD9002 will need to be equally fast. Whichever of the ECL logic families is used, special care must be exercised to keep digital switching noise away from the analog circuits around the AD9002. The two most critical items are digital supply lines and digital ground return. The input capacitance of the AD9002 is an exceptionally low 17 pF. This allows the use of a wide range of input amplifiers, both hybrid and monolithic. To take full advantage of the wide input bandwidth of the AD9002, a hybrid amplifier such as the AD9610 will be required. For those applications that do not require the full input bandwidth of the AD9002, more traditional monolithic amplifiers, such as the AD846, will work very well. Overall performance with any amplifier can be improved by inserting a 10 resistor in series with the amplifier output. The output data is buffered through the ECL compatible output latches. All data is delayed by one clock cycle, in addition to the latch propagation delay (tPD), before becoming available at the outputs. Both the analog-to-digital conversion cycle and the data transfer to the output latches are triggered on the rising edge of the differential, ECL compactible ENCODE signal (see timing diagram). In applications where only a single-ended signal is available, the AD96685, a high speed, ECL voltage comparator, can be employed to generate the differential signals. All ECL signals (including the overflow bit) should be terminated properly to avoid ringing and reflection. The AD9002 also incorporates a HYSTERESIS control pin which provides from 0 mV to 10 mV of additional hysteresis in the comparator input stages. Adjustments in the HYSTERESIS control voltage may help improve noise immunity and overall performance in harsh environments. The OVERFLOW INHIBIT pin of the AD9002 determines how the converter handles overrange inputs (AIN +VREF). In the "enabled" state (floating at -5.2 V), the OVERFLOW output will be at logic HIGH and all other outputs will be at logic LOW for overrange inputs (return-to-zero operation). In the "inhibited" state (tied to ground), the OVERFLOW output will be at logic LOW, and all other outputs will be at logic HIGH for overrange inputs (nonreturn-to-zero operation). The AD9002 provides outstanding error rate performance. This is due to tight control of comparator offset matching and a fault tolerant decoding stage. Additional improvements in error rate are possible through the addition of hysteresis (see HYSTERESIS control pin). This level of performance is extremely important in fault-sensitive applications such as digital radio (QAM). Dramatic improvements in comparator design and construction give the AD9002 excellent dynamic characteristics, especially SNR (signal-to-noise ratio). The 160 MHz input bandwidth and low error rate performance give the AD9002 an SNR of 48 dB with a 1.23 MHz input. High SNR performance is particularly important in wide bandwidth applications, such as pulse signature analysis, commonly performed in advanced radar receivers.
Designs using the AD9002, like all high speed devices, must follow a few basic layout rules to insure optimum performance. Essentially, these guidelines are meant to avoid many of the problems associated with high speed designs. The first requirement is for a substantial ground plane around and under the AD9002. Separate ground plane areas for the digital and analog components may be useful, but these separate grounds should be connected together at the AD9002 to avoid the effects of "ground loop" currents. The second area that requires an extra degree of attention involves the three reference inputs, +VREF, REFMID, and -VREF. The +VREF input and the -VREF input should both be driven from a low impedance source (note that the +VREF input is typically tied to analog ground). A low drift amplifier should provide satisfactory results, even over an extended temperature range. Adjustments at the REFMID input may be useful in improving the integral linearity by correcting any reference ladder skews. The application circuit shown below demonstrates a simple and effective means of driving the reference circuit. The reference inputs should be adequately decoupled to ground through 0.1 F chip capacitors to limit the effects of system noise on conversion accuracy. The power supply pins must also be decoupled to ground to improve noise immunity; 0.1 F and 0.01 F chip capacitors are recommended. The analog input signal is brought into the AD9002 through two separate input pins. It is very important that the two input pins be driven symmetrically with equal length electrical connections. Otherwise, aperture delay errors may degrade converter performance at high frequencies.
-15V 1k 4k 100 2N3906
0.1 F ANALOG INPUT (0V TO 2V)
AD741
NYQUEST FILTER 1.5k 40 50 EQUAL DISTANCE AIN
10 0.1 F
-VREF +VREF AIN OVERFLOW D8 (MSB) D7 D6 D5 D4 D3 D2 D1 (LSB)
AD9611
ENCODE INPUT (GROUND THRESHOLD)
AD9002
ENCODE 50 ENCODE
AD96685
-5.2A -5.2D
0.01 F
0.1 F
0.1 F
0.01 F
Figure 5. Typical Application
-6-
REV. F
AD9002
LINEARITY OUTPUT (ERROR WAVEFORM) RECONSTRUCTED OUTPUT
HOS100
1k
HOS100
50
-15V 1k 4.3k
3.75
AD741
150 0.1 F 2N3906 90 20 90
0.01 F 50
0.1 F
AD9768 DAC
HOS200
10 F ANALOG INPUT 50 2k
75
AIN EQUAL DISTANCE AIN
-VREF
REFMID
+VREF OVERFLOW D8(MSB) D7 D6 REGISTER 100151 LINE DRIVER 100114 37-PIN D CONNECTOR
AD96687
1k 3.9k 0.1 F
ENCODE ENCODE OVERFLOW INH
AD9002*
D5 D4 D3 D2 D1(LSB)
HYSTERESIS -15V 1k -5.2V 0.01 F 0.1 F 0.1 F 625 0.1 F -5.2A -5.2D
0.01 F
ENCODE INPUT (GROUND THRESHOLD)
AD96687
50 510 -5.2V
AD96687 AD96687
0.1 F DELAY 13k 1k -15V 880 510 -5.2V DELAY 13k 1k -15V 880
NOTE: 100114 LINE DRIVER OUTPUTS REQUIRE 510 PULL-DOWN RESISTORS TO -5.2V. ALL OTHER ECL OUTPUTS SHOULD BE TERMINATED TO -2V WITH 100 RESISTERS, UNLESS OTHERWISE SPECIFIED. RESISTORS ARE IN . CAPACITORS ARE IN F.
*CONTACT FACTORY ABOUT EVALUATION BOARD AVAILABILITY
Figure 6. AD9002 Evaluation Circuit
65
RMS SIGNAL-TO-NOISE RATIO (dB) AND HARMONIC LEVELS (-dBc)
60 55 50 SNR 45 40 35
2ND HARMONIC
3RD HARMONIC
30 10MHz 1MHz 100MHz ANALOG INPUT FREQUENCY (0.1dB BELOW FULL SCALE) 125 MSPS ENCODE RATE
Figure 7. Dynamic Performance
REV. F
-7-
AD9002
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic Side-Brazed DIP (D-28)
0.005 (0.13) MIN
28
0.100 (2.54) MAX
15
0.610 (15.49) 0.500 (12.70) PIN 1
1 14
1.490 (37.85) MAX 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) BSC
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.620 (15.75) 0.590 (14.99)
0.070 (1.78) SEATING PLANE 0.030 (0.76)
0.018 (0.46) 0.008 (0.20)
28-Lead Ceramic Leadless Chip Carrier (E-28A)
0.458 (11.63) 0.442 (11.23) SQ 0.100 (2.54) 0.064 (1.63) 0.095 (2.41) 0.075 (1.90) TOP VIEW 0.458 (11.63) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37)
19 18
0.075 (1.91) REF
26 25
0.300 (7.62) BSC 0.150 (3.51) BSC
4 28 1 5
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 45 TYP
BOTTOM VIEW
12 11
0.055 (1.40) 0.045 (1.14)
0.200 (5.08) BSC
28-Leaded JLCC (J-28)
0.171 (4.34) MAX
25 26
0.450 0.006 (11.43 0.152) SQ
19 18
0.039 (0.991
0.005 0.127)
BOTTOM VIEW
0.050 (1.27) BSC
PIN 1
TOP VIEW
(PINS DOWN)
0.300 (7.62) TYP
0.028 (0.711
0.002 0.051) 0.420 0.010 (10.668 0.254)
4 5 11
12
0.022 (0.559
0.003 0.076)
0.488 0.010 SQ (11.43 0.254)
0.102 (1.448
0.010 0.254)
0.006 0.0006 (0.152 0.015)
Revision History
Location Data Sheet changed from REV. E to REV. F. Page
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
-8-
REV. F
PRINTED IN U.S.A.
0.019 (0.483
0.002 0.051)
C00545d-0-9/01(F)

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